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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! Issues in changing baudrate of USART1 on the fly

Posted on July 02, 2018 at 11:00Hello,I am using an STM32F042 controller. I have to send a wake-up pattern followed immediately by 5 bytes (@10400 baud) from my device. Wakeup pattern: 25msec LOW followed by 25msec HIGH5 byte sequence: 0xC1, 0x11, 0...

How timers in STM32F7 start workig?

While preparing slides for students about timers in STM32F7 microcontrollers, I came across several inaccuracies in the description of their work presented in the STM32F7 reference manual RM0410 rev 4. The following sentence can be found in the menti...

MirKoz by Associate III
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TIMx_ARR relations to the preload and shadow register?

In RM0008 Technical Reference Chapter 15, TIMx_ARR was introduced in counting mode. Meanwhile, two other registers: preloaded and shadow register, were also mentioned. However, in the TIMx register Map, Preloaded and shadow registers were not mention...

KSun.11 by Associate II
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  • 3 replies
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Resolved! STM32F4 DSP noise with inbuilt ADC and DAC

I'm trying to perform signal filtering with STM32F407VGT. I've set up the ADC and DAC to work synchronously, triggered by a timer at 42kHz, and using DMA. The idea is to process half of the buffer while ADC is filling the other half. However, even wi...

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A_Dave by Associate
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Delay from CKT_EN to CK_CNT

In the RM0008, Figure 120 on page 379, it says "as soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock, CK_INT. " as shown below. However in the figure, the CK_CNT appears 2 cycles after the CEN bit became 1. Given t...

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KSun.11 by Associate II
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  • 3 replies
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