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CHead · 2019-11-14

My OTG_HS2 kernel clock is PLL3Q at 48 MHz. If I use CSleep (only CSleep, not any of the deep sleep modes), SOFs are generated at the wrong interval (checked with protocol analyzer and oscilloscope). If I remove the WFI, SOFs are generated at the pro...

CHead · 2019-06-03

it seems that a write to AXI SRAM very shortly before a system reset (via AIRCR) gets lost. I wrote a very short block of code that simply reads a word from 0x24000000, increments it, writes it back, and resets the processor. I can see that the value...

CHead · 2019-04-11

According to what documentation I can find, ECC is supported in the caches, the TCMs, the system SRAMs, and the Flash.For caches, the situation is simple: caches must be invalidated before being enabled (whether or not ECC is present), and the Corte...

CHead · 2019-03-22

According to reference manual section 49.4.7 (Slave select (SS) pin management), “Hardware SS management (SSM = 0): in this case, there are two possible configurations … SS output enable (SSOE = 1)�?.However, according to reference manual section 49...

CHead · 2019-01-10

In reference manual table 55 (Kernel clock distribution overview), there is a line for the DFSDM clock, indicating that it can be taken from either sys_ck or bus clock (which in the case of DFSDM would be APB2). That table also indicates that the max...

CHead · 2019-12-20

Clarifying comment: lots of other USB things, not just the SOF period, seem to be broken by CSleep.

CHead · 2019-09-16

In my case, yes. When I said I used the debugger, I mean I printed the memory by address, not the variable (which the debugger could have interpreted as a request to print a register instead).

CHead · 2019-06-05

Overnight test ran ~17,000 resets and rewriting the data that used to get corrupted at 64-bit size resulted in it not getting corrupted.

CHead · 2019-06-04

In a way, yes. It seems I misunderstood the sentence “When a half word is written to an internal SRAM and a reset occurs, this half word is not really written to the SRAM after reset. This due to the ECC behavior.�? I interpreted “half word�? using t...

CHead · 2019-06-03

In my real code, I *do* clean the D-cache before resetting. In my test code, I don’t even enable the caches.

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USB SOF period incorrect in host mode during CSleep on STM32H743

AXI SRAM losing last few writes across reset

What are the requirements for RAM ECC on the STM32H7?

Should SSM be 0 or 1 when using SSOE=1?

Can APB frequency be >133 MHz with DFSDM enabled if ACLK is used?

Re: USB SOF period incorrect in host mode during CSleep on STM32H743

Re: AXI SRAM losing last few writes across reset

Re: AXI SRAM losing last few writes across reset

Re: AXI SRAM losing last few writes across reset

Re: AXI SRAM losing last few writes across reset