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STM32G4 flash write/erase

I'm quite confused. The RM0440 states: "Note that read-while-write capability (or RWW) is only supported when the dual-bank architecture is active. This enables programming or erasing one bank while executing code from the other bank." Okay, for me, ...

BMcK by Associate III
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  • 16 replies
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stm32L452 HAL_SD_WriteBlocks_DMA without irq response

It is the problem about the dma driver of stm32L452's sdmmc1.ide: cubeideboard: NUCLEO-L452REconfig: sdmmc1 with dma , sd 4bit, without rtossdmmc1 dma config : 1. {sdmmc1 both(rx and tx) : dma2_channel_4} or 2. {(sdmmc1_rx : dma2_channel_4) and (s...

Cchn.1 by Associate II
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Debug infrastructure in STM32F7

For a long time I have been trying to guess how debug components are connected to the Cortex-M7 core in STM32F7 series of microcontrollers. It is supposed to be shown in e.g. the document RM0410 in Figure 587. This figure seems to be a copy of the sa...

MirKoz by Associate III
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Problems with TCP/IP Client not working on H743.

The server connects and communicates normally, and the Client experiences a return value = -13, Abort in the connect function.Using the Netconn API, the user program is hercles_3-2-8.exe. PC IP is 192.168.0.223 and Device IP is 192.168.0.222.The code...

CHan.2 by Associate II
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  • 1 replies
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Misprint in F4/G4 Programming Manual (Bitband)

There is a misprint in your PM0214 Programming manual "The Cortex M4 processor" in the chapter chapter 2.2.5 "Bit-Banding", above figure 9. Bit-Banding is nicely described there, but of course all bit addresses have to end by "00"... Your first exam...

flyer31 by Senior
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  • 14 replies
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Resolved! What's the difference between I2C SWRST and ABPxRSTR reset

I have a bug in the I2C bus where sometimes a glitch causes the BUSY flag to be setI found that the only ways to clear it is either by SWRST in I2C->CR1 or by resetting in RCC->ABP1RSTR->I2CxRSTRMy question is, is there any difference I should know a...

AAl-H by Associate III
  • 1810 Views
  • 3 replies
  • 1 kudos