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I am using a STM32F407, and I would like to use DMA to receive data from USART1 and store in a buffer.HAL is not being used.USART1 is configured and is receiving the first byte of the message correctly. That is, the data shows up in USART1->DR.Here i...
I took the driver from Arduino for ADS119X and implement the HAL code for STM.When compiling, it gives me “undefined reference to `keepSetting'�?. First I tought on a code problem but after long time of trail and error, I was looking on forums. It’s ...
Hi, I want to be able to add CAN message with "HAL_CAN_AddTxMessage" from interrupt and main loop (loop maybe busy sometimes so I cant send all messages from it). I assume they can collide and override so its not safe to do it from both?What are my o...
I've been trying to configure a TIM6 to run at 48kHz, where APB1 is 108MHz, but because the APBDIV > 1, I used PSC = 449, and Period = 9:216,000,000 / ((449+1)*(9+1)) = 48,000And in my timer interrupt, I set a GPIO output pin to toggle. When I probe ...
I'm testing STM32L051C8T6 without any peripherals or extra electronics. No crystals used.After reset and first power down I get about 1.40uA. the MCU wakes up and powers down and then I get about 3uA in power down mode. After changing all kind of cod...
I was working with SPI dma transmision. I config two channels for transmit and receive, however I didn't enable interrupt option in dma, however, before each transmision I cleared tc flag, and then enable spi while polling the tc flag. This works rea...
Use two NUCLEO-H743ZI boards for SPI communication. Full-duplex DMA mode. When the baud rate is 25M, the master and the slave can receive the data correctly. At 50M and 100M, the slave can receive the data correctly, but the master cannot receive the...
Hello, In India, the STM32F407 discovery board is out of stock. I enquired many vendors like element14, Digikey and other locals, it's not at all available. Did ST stop the production of this ? Will it be availabel in the future ? which is the close ...
Hello there.Our design currently utilizes MDMA for intensive writes from SRAM4 to FMC bus area. Transfer is setup with double word transactions, witch is critical for performance. DMA 1/2 or BDMA is simply do not cut it due to lack of AXI access i gu...
