Hardware trigger for MDMA?

[BStud.1]

Hello there.

Our design currently utilizes MDMA for intensive writes from SRAM4 to FMC bus area. Transfer is setup with double word transactions, witch is critical for performance. DMA 1/2 or BDMA is simply do not cut it due to lack of AXI access i guess. When I switch from MDMA to DMA1/2 or BDMA performance halves roughly by 2. But we do need to restart transaction right after it finished. Unfortunately MDMA cannot trigger itself as far as I understand. Even linked list mode requires each element to be triggered by something. It can only be softwaretriggered or triggered by a limited trigger table.

How do I keep my write performance and make MDMA auto restart transaction?

I think i can hack in some Timer and DMA1 together to serve as trigger for MDMA but this is looks like a hack rather than a solution. Is my understanding of MDMA triggering correct?

Thanks

EDIT:

The chip in question is STM32H750. But i think only H7 series have MDMA onboard.

EDIT2:

Looks like in page 9 of this doc: https://www.st.com/content/ccc/resource/training/technical/product_training/group0/5a/1c/4e/96/b8/23/40/3c/STM32H7-System-Master_direct_memory_access_controller_MDMA/files/STM32H7-System-Master_direct_memory_access_controller_MDMA.pdf/_jcr_content/translations/en.STM32H7-System-Master_direct_memory_... it is possible to setup loop transfer that mut be triggere once by sofware and that is it. But it iseem i can not setup this via STM32CubeIDE.

[waclawek.jan · Accepted solution]

I don't use the 'H7 but it appears that yes, setting TRGM=0b11 and using a looped-back linked-list should result in infinite transfers. I don't think it's a good idea (among other things continued DMA impacts performance of the rest of the system), you may want to rethink your application.

There will probably be some small delay in the observed writes on FMC, while the registers reload from the linked-list and MDMA restarts.

> But it iseem i can not setup this via STM32CubeIDE.

Then set it up normally, directly writing to registers.

JW

[BStud.1]

So I was able to circle up my MDMA transfer and it is working fine. The key thing was MDMA's LAR register. Address that it points must aligned by 64 bits and must lie in AXI memory space. @Community member​ Yeah, this is pretty stupid architecture but it is not my call to change it now. There is some register reload delay, but it is relatively constant and in orders of magnitude shorter than software reloading. Cheers.

[waclawek.jan]

Thanks for coming back with your findings.

JW