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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! RTC inaccuracy induced by internal clock source?

I'm using the STM32L431xx mcu. The current hardware configuration of our design has no external clock source (crystal), so we are using the internal one. And there's a new functionality which demands second-accurate real time clock, over a period of...

I2C in DMA mode - deadlock on I2C interrupt

Has anyone have similiar issues ? I got I2C DMA writes working nicely on table, but in real application there are disturbances which cause false start condition on the bus.This happen when I2C HAL driver has "lock" on I2C handle - so incoming interr...

Forcing Capture-Compare-Register to clear [STM32H7]

I'm trying to count the number transition during the time another process is taking place. Don't need frequency, just the counts.So I've enabled TIM8CH3 for capture-compare, and have verified that CCR3 does change when there are transitions on th...

bnguy.1 by Associate III
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Interrupt mapping to NVIC ISR vector

I was looking at the ARM M7 reference manual, and it shows an empty NVIC ISR vector from 0x40 to 0x3fc. When I look at the file startup_stm32h725xx.s it defines specific interrupts mapped to the ISR vector. Are these hard mapped by the EXTI block an...

DCons.1 by Associate
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Resolved! STM32H7 Hard Fault when RCC at 165 MHz

I have the STM32H7B3I-DK (MCU: STM32H7B3LIH6Q), and I am trying to get the sys_ck close to its maximum frequency of 280 MHz, by running HSI or HSE through PLL. The trouble is that I can only get up to 164 MHz. Any higher and I get a hard fault. Is th...

FSkro.1 by Associate II
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