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Resolved! How does AHB Prescaler value fill? const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

I want to know what kind of value we fill in this and what affects the AHB Bus please make me understand.const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};I tried to find out but only figured out the value of 1 to 9 i...

PKuma.9 by Associate II
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Resolved! Bitwise

"I'll delete this question once someone answers it, as it is not relevant".Why in second line did some one write ch & 0xFF? ch limits are already 0 to 255 right?

0693W00000QMqCCQA1.png
Vmere.1 by Senior
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  • 4 replies
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STM32G4 op amps (>1) as inverting PGA with mid-point bias applied to non-inverting inputs - tie non-inverting inputs together?

Application needs to use all three (in STM32G431) op amps as inverting PGA handling ac-coupled signals. As there's no internal option to supply mid-point (VREF/2 with a decoupling cap at the device pin) to the non-inverting inputs of the (3) op amps ...

wb0gaz by Senior
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Stm32f4 Generate pwm signals via external trigger signal

Hi, i have a sensor that generates a TTL signal. I need a couple Pwm signal by using this external signal which is my master. I have Stm32f4 discovery MCU​ . Is there any way to do this goal. Please help me with any code sample or documents.

AAlk.1 by Associate
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  • 0 replies
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Resolved! STM32F413 flash erase doesn't work first time

Hi,I am using STM32F413 Nucleo board. I am using MDK5 IDE and HAL libraries. I made an example for reading/writing internal flash based upon a cube project. The idea is to erase interal flash and then to write some data to it. I alreay did some simil...

Nix Wayne by Associate III
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  • 9 replies
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error 0xfffffffe

I am writing a Programm on stm32cubeide. But during Debugging and Running the Programm, I habe the error Break at address "0xfffffffe" with no debug information available, or outside of program code.I don't know what it means and can I handle with th...

TGill.2 by Associate
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  • 2 replies
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stm32h750vbt6 DMA is not working if active D cache

I have read previous posts ,,,I set up dma to read adc ,Although dma's destination address is allocated from AXI RAM, dma does not work when d cache is active.Can anyone share detailed information or a sample code about this?