STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
Hello,I want to implement the SNMP agent based on standalone, not based on os.I could have got a example code for snmp agent?Thank.
I need to configure one of the USART peripherals in STM32F0 series MCU without using HAL or Low-layer drivers. I plan to fully initialize and drive the USART peripheral registers directly from the application, including assigning the USART to the req...
The project I am refering to is using a stm32L562QE mcu with a W25Q32JV nor flash external memory OCTOSPI.W25Q64JV is running in Memory mapped mode otfdec is enabled. ICACHE is enabled with burst mode set to wrap.I am trying to configure the octospi ...
Hello,I'm trying to set up the character match interrupt to detect the character '\n' (which indicates the end of a packet) and I don't manage to get the interruption.The procedure I'm using is:initialize the uart, its gpios, and the dma.enable the u...
Hi,From the errata sheet I have seen, that the STM32F7x2 has a problem with the cache in write through:Errata:https://www.st.com/resource/en/errata_sheet/es0360-stm32f72xxx-and-stm32f73xxx-device-limitations-stmicroelectronics.pdfDatasheet:https://ww...
Is it possible in the STM32 world to have two synchronized PWM - but with an offset separating the outputs?Here's the problem in picture form:Both the blue and red traces are the same frequency and duty cycle, but in this case trace red is offset 50 ...
Dear Madame or Sir.We found some errors in HAL-Driver "stm32h7xx_hal_fdcan.c" Version 1.10.0.0:for the FDCAN modul of STM32H743.stm32h7xx_hal_fdcan.cA call of the function "HAL_FDCAN_DeactivateNotification" and"HAL_FDCAN_TT_DeactivateNotification"CAN...
STM32H743Does errata 2.16.2 "Wrong data may be read from Message RAM by the CPUwhen using two FDCANs" apply to silicon revision V?The errata indicates it does, but previous discussion by Imen Dahmen indicates the issue was corrected. I need a confirm...
The errata sheet of these MCUs says:2.16.2 Wrong data may be read from Message RAM by the CPU when using two FDCANsDescriptionWhen using two FDCAN controllers, and the CPU and FDCANs simultaneously request read accesses from Message RAM, the CPU read...
Hi, I always appreciate all members here for helping beginners like me :)I am currently working on a project using Timer and ADC+SPI with DMA.The main timer loop is running at 40kHz, and this frequency should be strictly guaranteed.Two DMA process...
