Ask questions, find answers, and share insights on STM32 products and their technical features.
I have an STM32L100C-DISCO board (MB110B Rev. B) and I want to install the LSE crystal, which is not populated by default. I consulted the schematic in the UM1656 "user manual for the 32L100CDISCOVERY discovery kit". Crystal X3 has a part number of...
test code as below:#include <rtthread.h> #include <rthw.h> #define CPU_USAGE_CALC_TICK 100 #define CPU_USAGE_LOOP 100 static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; static rt_uint32_t total_count = 0; static rt_uint32_t _c...
Dear All,I am trying to develop a code for STM32H742VGT revision V. ADC1 and ADC2 work in regular simultaneous mode and they are set to convert 6 channels. All the settings are exactly same to have same sampling and conversion time. Of course, ADC1 a...
I´m using the SPI1 via the alternative pins PB3-PB5 and I'm experiencing various issues. I have previously used the STM32F722 with somehow same CubeIDE setup and code and that works perfectly.I have made a simple test application that only sends one ...
Hey Folks.So, I have the H757I-Eval Board that I got as a gift, and given that I'd like to try some stuff and even follow some tutorials, I miss the exposition of the PINs. Reading TN1238 which talks about a fan-out expansion board, it says "The prin...
I am making this call: if(HAL_SPI_Receive_DMA(&hspi3, &aRecvBuffer[0],3)!= HAL_OK)inside an external GPIO interrupt handler that gets called every 20 us. It is used to read data from an external ADC. I noticed that this dma transfer works well only ...
I'm trying to follow the OSPI_NOR_MemoryMapped STM32CubeIDE example, but for a different device (W25Q128FV). Write Enable, Read Status, and Erase Sector commands behave as expected, as well as memory-mapped reads. This has been confirmed by monitorin...
Code isn't complex, hence i don't understand what could be the problem.char pin_status;pin_status=HAL_GPIO_ReadPin(SENSOR_H1_GPIO_Port,SENSOR_H1_Pin);
Usually peripherial SPI drivers support 3 delays to control signals timing:Delay from SS enable edge to first SCK edge (SS Idleness) - supported in STM32H7xxDelay between data (Inter-data Idleness)- supported in STM32H7xxDelay after SCK edge to SS d...
