STM32 MCUs products

cancel
Showing results for 
Search instead for 
Did you mean: 

Forum Posts

New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

gif-stm32u0.gif

STM32L4 ADC does not stop

Hello,According to the Reference Manual of the STM32L431 controller, the ADSTP in the ADC_CR register must be set to 1 to stop the ADC. Additional condition is that both ADSTART=1 and ADDIS=0 must be. Once the ADC is stopped, the ADSTP bit is cleared...

user 143 by Associate III
  • 333 Views
  • 2 replies
  • 0 kudos

boot application - issue with SCB_DisableDCache

does anybody have a idea why the code is stuck at below do while loop (bold marked)?.use case: for the boot application , SCB_DisableDCache () is getting called before jumping into use aplication.__STATIC_INLINE void SCB_DisableDCache (void){ #if de...

Anand Ram by Associate III
  • 1620 Views
  • 14 replies
  • 1 kudos

SPİ SCK frequency ?

hello , I use spi and ı use slave mod spi. When I send a frequency of 500khz or more as a clock so data is shifting or I recieve wrong data but I send a frequency less than 500 khz I recieve true data. what is the reason of this.( use stm32h743z...

Resolved! STM32L4R: How do Flash Option DBANK and DB1M interacts?

In FLASH_OPTR, both DBANK and DB1M are r/w and have no restrictions beside that PCROPA/B needs to be disabled. For 1M device there are two(?) sensible settings DBANK=1, DB1M = 1 for 1Myte dual bank continous modeDBANK=0, DB1M = 0 for 1Myte single ban...

Labels