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rwareinc · 2024-06-20

Specifically, I require a timer for creating a clock to a peripheral. I chose PH5 (Timer12 Channel 2) because of the allocation capability in CubeMX, however, the datasheet for the STM32H757 does not show that as an alternate function.I have confirm...

rwareinc · 2023-03-28

I refuse to purchase a $40 chip for over $400 dollars so will not purchase on current market. I based an entire product line on the STM32H757 and now I cannot buy them so the real question is, should I move to a different processor?

rwareinc · 2022-12-23

Should I give up on the STM32H series and move to the STM32MP series?

rwareinc · 2020-06-03

rwareinc · 2019-09-22

rwareinc · 2024-07-03

Sorry, PH9 is the pin I wanted to target...

rwareinc · 2024-07-03

Thank you for taking the time on this subject, I will make an assumption that if you are stating Table 16 needs correction, then time timer AF exists on the pin PH5 and it is safe to design that way?

rwareinc · 2024-06-20

The post actually pertains to PH9.

rwareinc · 2024-06-20

Appreciate your comment, I usually trust the datasheet, however, some of the related chips, i.e. STM3274x have very similar layouts and do document the AF codes for PH9 to Timer12, this is what gives me hope. It's just another trace but the re-desig...

rwareinc · 2023-03-29

Kaouthar,Thank you for taking this on, I have been an ST fan and customer for 20+ years and it is great to get support like this.

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STM32H757 Datasheet missing information

Cannot find a single STM32H7 series chip at any of the standard sellers in North America while the STM32MP series can be found anywhere, so my question is;What does support, in terms of manufacturing, of the STM32H7 look like in the future?

I cannot locate the STM32H757 chips for sale anywhere, at least not at anything below extortion level prices. On the other hand the STM32MP1xx series are available everywhere and are still at reasonable prices. Is this a push to shift technologies?

DMA sets NDTR to 0xffff when enabled even when peripheral (SPI1 rx) is not enabled or has DMARX set. All memory is in D1 (AXI) and peripheral is working using interrupts.

Is there a preferred method for communications between the M7/M4 cores? One that can wake a core from deep sleep mode?

Re: STM32H757 Datasheet missing information

Re: STM32H757 Datasheet missing information

Re: STM32H757 Datasheet missing information

Re: STM32H757 Datasheet missing information

Re: Cannot find a single STM32H7 series chip at any of the standard sellers in North America while the STM32MP series can be found anywhere, so my question is; What does support, in terms of manufacturing, of the STM32H7 look like in the future?