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I'm looking for information that will tell me the safe clock speeds for a voltage range. For example from 1.8v to 2.5v what is the highest clock speed I can run safely. usually there is a figure in the datasheet, but I can't find it. I'm using a ...
Unfortunately, I cannot post any code for this question but I believe it relates more to the HAL library and the i2c address matching hardware of the STM32 microcontrollers.I am working on emulating multiple I2C slaves in the address range of 1-24 on...
Hello dear friends,It's been a week since I worked on the CAN transceiver and couldn't make it work. I have set up the chip rcc, bit rate, and receive interrupt of CAN, set the receive filter, and the receiver id in transmission, with no success. I h...
i'm using STM32F030F4Px for MODBUS Master Slave communication based on USART (RS485 communication). i'm using 9600 baud rate, 8bit 1 stop bit communication with DMA and HAL. Master is transmitting 8 bytes to slave after 10 or 20 msec which are receiv...
For reference I have a nucelo G491RE board. Aim : I am trying to connect 4 sensors which have a low output signal to be amplified and then sampled by 2 ADCs (2 sensors are connected to one ADC). The problem is, is that I need a really high sampling r...
I run the debugger with error on the first attempt. On subsequent attempts the debugger pops up a "problem Occurred" dialog box that says;Debugger Update Job has encountered a problem.An internal error occurred during; "Debugger Update Job"Opening t...
Hello everyone,I'm working on a STM32L4 project which embeds a QSPI external Flash Memory (not yet sourced but doesn't matter).This QSPI Flash Memory would be splitted into 2 parts, one for TouchGFX Images and one for 10MB Filesystem. This FS will ha...
Shall I go ahead with this part or can someone suggest an alternative which is available off-the-shelf or with reasonable lead times
Bugs in STM32G4, RM0440 Rev 7 for FDCAN:1)STM32G4, RM0440 Rev 7 44.3.3 Message RAM.It is written on the page 1953:"In case of multiple instances the RAM start address for the FDCANn is computed by endaddress + 4 of FDCANn-1, and the FDCANn end addre...
