When SPI in Mode 3 is there a way to set the SCK or clock signal high before the first SPI transaction?
The L6474 uses SPI in MODE 3 where CPOL = 1 and CPHA = 1My logic analyzer is saying that having the SCK low when the CS is pulled low or enabled the idle state of the CLK (a.k.a. SCK) is not correct for MODE 3. After the first transaction the SCK st...