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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Why does MemManage Fault occur in ITCM?

Hi,​​MemManage Fault occured in ITCM when I changed the system clock and DMA channel.Does ITCM cause errors? What are the causes of errors? Any ideas?​I changed below:system clock: 480MHz→400MHzDMA: DMA2_Stream1 →BDMA_channel0

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Mapyam by Associate II
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[STM32F427] SPI with both DMA and classic use

Hello Everyone,I would like to ask you if you have any more information about an issue I'm incurring in.I am trying to setup a project on a custom board with the forementioned MCU, on which I need to use the first 4 SPI interfaces with DMA for quick ...

IDe S.1 by Associate
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Can't modify SCB register and Ethernet hard fault

Hi All, I'm using STM32H743ZI2 Nucleo board to connect to internet but I have a hard fault error.I'm try enable MMARVAILD bit in SCB->CFSR to hold valid fault address (SCB->CFSR |= (0X1UL<<7);) but it's still 0 after set command.Please help me to che...

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Dynamic Memory Allocation causes hard fault

I am trying to implement a function that extracts mfcc of the retrieved sound. I am using Hanning window. I actually am applying dynamic memory allocation twice. First allocation works successfully. Second allocation however somehow takes me to hard ...

Every time i getting the same error and i cant fix it . I am trying to write my uart communication as a header file even if i used the extern but it doesnt work , Can somenone help me how to write properly ?

09:32:54 **** Incremental Build of configuration Debug for project uart_deneme ****make -j8 all arm-none-eabi-gcc "../Core/Src/myHeader.c" -mcpu=cortex-m0 -std=gnu11 -g -DDEBUG -DUSE_HAL_DRIVER -DSTM32F072xB -c -I../Drivers/STM32F0xx_HAL_Driver/Inc -...

ÖBekt.1 by Associate
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What is the correct initialization order of GPIOs as alternate function output and associated peripherals in order to have full control over the state of the output pins?

We are currently working with STM32F103VE MCU and we have a dilemma about the order of initialization GPIO pins as alternate function outputs and associated peripherals. The goal is to have full control over the pin states. We have checked order of i...

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NMiti.3 by Associate II
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