Hello,
I have a STM32H75x design and suffer from read errors in DDR timing, no matter if run at 50MHz or slower.
It seems that the data hold time of 1ns the H7 is violated. The data output hold time of the SPI NOR MX25L12845 flash is 1ns, which seems to be too short for H7. Due to the fact, that the clock edge takes also ca. 0.5-1ns, the timing should be safe in my opinion. Nevertheless, a read failure arises if the drive strength of the flash is lower than 45Ohm and GPIO pin speed is higher than MEDIUM.
The H7 evaluation boards are equipped with Micron flash with 1.5ns and it seems that this value is fine for H7.
Therefore I doubt the data input hold time of 1ns@3.3V in table 181:
In my opion, this value should be longer than 1ns. Any user experience?
Thank you,
Jochen
Hello @KDJEM.1 ,
no, it isn't activated. If activated the write fails. As I understand, DHHC affects H7 write operation timing, but I suffer from H7 read error.
I should have mentioned that MX66L1G works fine on my HW, no matter which H7 GPIO speed is set (MEDIUM, HIGH, VERY HIGH) and flash driver strength (90-15 Ohm).
The MX25L128 fails on all 4 boards tested if flash drive strength is set to 30 Ohm. If set to 15 Ohm, even the auto status byte polling fails on write enable set command. I can watch the correct data on the scope but the H7 seems to recognize an incorrect bit pattern. Seems the high drive strength causes the H7 to fail.
Seem like there is kind of timing incompatibility between the H75x and MX25L128 but I cannot find a difference in the flash data sheets to blame for.
MX66L:
MX25L:
ODS(0,0) = 30 Ohm results in flash memory read error.
ODS(1.1) = 15 Ohm results in status register read error.
The calculated inductivity load is about 10pF.
The flash output hold time is on both flash 1ns but I guess that the value for MX25 is shorter than for the MX66.
