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Using Nucleo-U545RE-Q, SPI2 Full-duplex Master, default GPIO selected by STM32CubeMX v6.15.0 with LL selected for implementation.Config clock for max 160 MHz and prescale SPI by 8 for 20 Mbps. Add GPDMA Ch2/3 for SPI2 TX/RX.I double checked the outpu...
Hello,I am experiencing an interesting problem on the STM32F303VET:UART1 is used to receive and transmit messages (460800 Baud), DMA1 Channel 4 is used for memory to UART TX buffer transfer, DMA1 Channel 5 for UART RX buffer to memory transfer.Under ...
Reply to you How to fix SDIO error HAL_SD_ERROR_RX_OVERRUN? - STMicroelectronics Community SDIO data region should be AXI SRAM.
Hi Team,As we are going to use RAM – IC CY62136EV30 (TSOP-44) in our new project with ST micro STM32F407ZG (LQFP-144).Do we need any impedance matching for 6-layer board?Can you please suggest the same. Crystal frequency we taken 16MHz for the MCU.Th...
System OverviewHardware ConfigurationMicrocontroller: STM32H7S3L8H6Memory ArchitectureXSPI1 (Flash, MX25UW25645GXDI00): 32MB, accessed via GPIOP/GPIOOClock: PLL2S source, Prescaler = 3flash_xspi_handle.Instance = config->instance; flash_xspi_handle.I...
I am having a custom board having STM32N657I0H3Q interfaced with quad flash MX25R6435FM2IL0. I am unable to access (both read and write) to the flash MX25R6435FM2IL0.I have attached Saleae capture (configured the flash in single mode only for Saleae ...
Hi,we are trying to get a 800x800 display to work with the STM32U5G9VJT6Q, using either RGB888 or RGB565 in Video Mode (Burst).According to what we read it is definitely possible. Did we miss something?Could someone please confirm that is definitely ...
I am trying to create two phase-shifted PWM waves on an STM32L4 TIM1 using asymmetric mode. From what I understand, I have to:enable output on GPIO channels 1 and 3enable output compare 1,2,3,4 and output compare 1,2,3,4 as asymmetric PWM modeThen, I...
From the ES0335 errata there are two errata that look pretty significant for dual bank boot (which I'm planning to use as the basis of field firmware update):2.2.8 Dual-bank boot not working when the boot in flash memory is selected by BOOT0 pinDesc...
Hi,I am working on an application for the STM32N6 (using zephyr) that streams data from four SPI interfaces (SPI1, SPI2, SPI3 and SPI6) via Ethernet (UDP). I am using full-duplex SPI transfers and GPDMA1.Everything works fine up to SPI clock frequenc...
