2025-07-06 9:57 AM - edited 2025-07-06 10:00 AM
Hello - I recently took a working design and upgraded from the STM32L4 to the STM32L5. I'm having a major issue getting the i2c bus to work properly.
Here is the design, I've highlighted PB10 and PB11. Not visible in this is the 4.7 kOhm pull up resistors, but you'll have to trust me, they are there (just in a different part of the design)
Here's a picture of the board with the pull-up resistors visible:
And here's my pin configuration for PB10/11
I've also attached a copy of a simple Cube IDE program you can compile and run which performs an i2c scan. However, the scan files because both SDA/SCL remain at 0.8V and 1.0V the whole time and are never allowed to pull high. These numbers don't even make sense - why 0.8V and 1.0V?!
Things I've tried:
I don't know what more to do or what more to look into. I've read the errata for L5 and nothing stands out. Trustzone is definitely disabled, so I can't see why anything would override it here. I would appreciate any tips or leads because this is now completely blocking our project. Thank you in advance!!
My option bytes are below:
OPTION BYTES BANK: 0
Read Out Protection:
RDP : 0xAA (Level 0, no protection)
BOR Level:
BOR_LEV : 0x0 (BOR Level 0, reset level threshold is around 1.7 V)
User Configuration:
nRST_STOP : 0x1 (No reset generated when entering Stop mode)
nRST_STDBY : 0x1 (No reset generated when entering Standby mode)
nRST_SHDW : 0x1 (No reset generated when entering the Shutdown mode)
IWDG_SW : 0x1 (Software independent watchdog)
IWDG_STOP : 0x1 (IWDG counter active in stop mode)
IWDG_STDBY : 0x1 (IWDG counter active in standby mode)
WWDG_SW : 0x1 (Software window watchdog)
SWAP_BANK : 0x0 (Bank 1 and bank 2 address are not swapped)
DB256 : 0x1 (256Kb dual-bank Flash with contiguous addresses)
DBANK : 0x1 (Dual bank mode with 64 bits data)
SRAM2_PE : 0x1 (SRAM2 parity check disable)
SRAM2_RST : 0x1 (SRAM2 is not erased when a system reset occurs)
nSWBOOT0 : 0x1 (BOOT0 taken from PH3/BOOT0 pin)
nBOOT0 : 0x1 (nBOOT0 = 1)
PA15_PUPEN : 0x1 (USB power delivery dead-battery disabled/ TDI pull-up activated)
TZEN : 0x0 (Global TrustZone security disabled)
NSBOOTADD0 : 0x100000 (0x8000000)
NSBOOTADD1 : 0x17F200 (0xBF90000)
BOOT_LOCK : 0x0 (Boot based on the pad/option bit configuration)
Write Protection 1:
WRP1A_PSTRT : 0x7F (0x803F800)
WRP1A_PEND : 0x0 (0x8000000)
WRP1B_PSTRT : 0x7F (0x803F800)
WRP1B_PEND : 0x0 (0x8000000)
OPTION BYTES BANK: 1
Write Protection 2:
WRP2A_PSTRT : 0x7F (0x807F800)
WRP2A_PEND : 0x0 (0x8040000)
WRP2B_PSTRT : 0x7F (0x807F800)
WRP2B_PEND : 0x0 (0x8040000)
Solved! Go to Solution.
2025-07-06 1:24 PM - edited 2025-07-06 1:28 PM
> STM32L562RET6
Close! Actually it’s STM32L562RET6Q. you can see the marking in your photo.
Sounds like you have an SMPS chip. Should be a Q at the end of the part number. These pads are not PB10/PB11 but rather SMPS pads.
2025-07-06 10:22 AM
With NRST held low, are they still at 0.8 V / 1.0 V?
If initialized as gpio outputs, can they be set to 0 / 3.3 V?
2025-07-06 12:49 PM - edited 2025-07-06 12:59 PM
Thank you for responding so quickly!
The only thing I can think of is that my PCBA shorted some pins under the MCU or something, but I can't think of which pins would show 0.8V or 1.0V to be able to even check. None of the neighboring pins provide any clues, so I'm not even sure how to complain to my PCBA
The chip I am using here is the: STM32L562RET6
2025-07-06 1:24 PM - edited 2025-07-06 1:28 PM
> STM32L562RET6
Close! Actually it’s STM32L562RET6Q. you can see the marking in your photo.
Sounds like you have an SMPS chip. Should be a Q at the end of the part number. These pads are not PB10/PB11 but rather SMPS pads.
2025-07-06 6:59 PM
OMG my PCBA put on the wrong chip 🤦 You are 100% correct. Thank you so much.