STM32 MCUs products

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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...


How to properly configure ADC injected group?

Hello, I've tried to use ADC for two Potentiometers only with injected group conversion but couldn't make it work. I'm using STM32F446RE. I couldn't find solution so I'm asking here. Previously I read their value correctly via polling and I know that...

Where can I find the relation between the OSPEEDR register different value (Low, Medium, High and Very High) and the frequency of the signals I want to use?

Hello ST Microelectronics community,I'm using a STM32H743ZI and I'm currently working on configurating properly the different I/O I want to use.To do so I need to set the set the pull up/down, open drain,etc. And also the speed mode.I could not find ...

BNord.1 by Associate III
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STM32l073RZ dual boot, bank 2 not work.

Dear.I work with stm32l073RZ and I have a blinking led code and that code works on bank1, but it doesn't work on bank2. The strangest thing is that I also used the sample code for a flashing led from stmcubel0 and it worked. I think it may be because...

About the calibration of the ADC on STM32H747

I am currently trying on the linearity calibration and I am following the protocol (down below) but I do not understand where I am supposed to get the saved linearity correction factor bits[159:150] (step 3)? Every single ADC register is 32 bits at m...

HTess.1 by Associate III
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STM32F412R HSI clock calibration with LSE

Hello,I'm looking for a way to calibrate HSI by using LSE. I've found some documents that describes the way. My situation is a little bit tough. I can't change PCB and I can't draw a way from LSE to TIM5 - channel 4. I'm looking for a way which will ...

OOzka.1 by Associate
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I use STM32H735 and her backup memory at 0x3880_0000 (4KB). All works OK if I use SCB_CleanDCache_by_Addr(0x38800000, 4096) after a write. Is it possible to disable dcache in this area ?

I tried to configure MPU using standard configuration generated.I tried this codeMPU_Region_InitTypeDef MPU_InitStruct;   HAL_MPU_Disable();   /* Configure the MPU as Strongly ordered for not defined regions */ MPU_InitStruct.Enable = MPU_REGION_ENAB...

PMina.2 by Associate
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SCK Active during CS High

I'm making use of the STM32L433 and using SPI to communicate with a LLCC68 from Semtech.I've noticed that my SCK is active after my CS goes high.Is this normal behavior?Code Snippet for SPI Write:LLCC68_StatusTypeDef spiWrite(uint8_t* data, uint8_t s...

STayl.3 by Associate II
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