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What is the correct way to read high cycle flash data.When i read address 0x916800 i get a Hard fault. Clearing and writing the this address works fine.With reading i have a problem. bank 2 has EDATA enabled for the last 2 pages. Can you give me a co...
Hello,I’m currently working on integrating the HX711 load cell amplifier with my NUCLEO-F767ZI development board. However, I’m having some difficulty determining which GPIO pins to use for the SCK (clock) and DT (data) lines.As I’m relatively new to ...
The TI motor drivers mct8329a and mct8316 require 100us delay between i2c data bytes. This can't include the acknowledge bit, but requires holding down the clock between transfers for the 100us. it is due to a bug in the TI chips that can't stretch c...
Dear all,I have dev a custom board pcb based on stm32h743ii with 32MB of flash and 32MB sdram FMC for a 7 inch lcd HD. I am new on cubeide i coming from esp32 world and i have some programing dev question .Is it a good idear to implement :To parti...
Hello, I am using QuadSPI in STM32H723ZGT6 which has OCTOSPI and I am changing octospi to quadspi in pin configuration and writing code also I had written same code for STM32H750VBT6 which only supports QUADSPI and I am using W25Q128JVSIQ Flash for t...
I am working with the STM32U5G7 microcontroller and have successfully implemented entry into STOP2 low-power mode. My system clock is 80Mhz(HSI, PLL), However, upon wake-up triggered via LPTIM . LPTIM is configured as counts internal clock events wit...
求一个demo
Pin 2 is connected to Boot0. is it Okey to do this (not using resistors).?
Dear STM Community and Experts,we are trying to implement a dual-port USB-C design using STM parts with the following requirements:Port 1: USB-C Power Delivery (PD) Sink, 100W, no dataPort 2: USB-C non-PD Source 5V 2A max., USB 3.1 Gen 1 Data, Displa...
