When the MCU is powered on or off, the GPIO will output a pulse at that moment.

[Haixiang]

Greetings,

During the power-on and power-off processes of the STM32F407 chip, the GPIO used as the DAC output will be pulled high for 8ms. The goal is that the GPIO should remain low when there is no DAC output. Adding an external pull-down resistor has an effect but cannot completely eliminate it. It was not present during online debugging, only occurring when there was a power surge. After erasing the program, it still existed. Preliminary judgment is that it is a hardware issue. Is there any way to solve this problem?

Thank you so much for the help. @KDJEM.1 @LPetr.1 @TDK

[Haixiang]

1.Is there any difference between VDDIO and VDD? Will the power-on of VDDIO earlier than VDD cause this problem?

2.Does VCAP handle the situation that causes this problem?

[TDK]

What chip exactly? What GPIO exactly?

Was an external pulldown resistor hooked up during the scope plots you took?

[mƎALLEm]

Hello @Haixiang and welcome to the community,

What do you mean by VDDIO? VDDIO separated power supply is not present on STM32F407 . Only newer products such as STM32H5 and STM32N6 have this separated power supplies for the IOs.

You said: "It was not present during online debugging, only occurring when there was a power surge. "

What if you disconnect the DAC output from U26 pin 3? do you have the same behavior?

[Haixiang]

Thank you for your reply.

1.The chip is STM32F407VGT6. The GPIOs PA4 and PA5 are used as two DAC outputs. I have initialized them as regular IOs with pull-down mode.

2.No external pull-down was added during the process of taking the oscilloscope image. The external pull-down flyline test showed some effect but it couldn't completely eliminate the problem. Without adding the external pull-down abnormal pulse of 2V, there was still about 1V remaining.

[Haixiang]

Thank you for your reply.

VDDIO is because I saw on AI that if it is powered on earlier than VDD, the GPIO state will be uncertain. If the power supply of STM32F407 does not have such distinction, then it is not caused by this reason. I tried to disconnect the PIN3 pin of U26, and the result was the same.

[Haixiang]

Currently, I plan to add a switch behind AOUT and control it via IO. After the microcontroller has stabilized its operation, it is closed. When the power is off, it is disconnected to prevent abnormal output from the I/O ports. However, I know this is not the root cause of the problem.

However, there is also a risk that controlling the IOs might cause instability during power changes. So, I'm considering using the NRST signal as the switching signal. Is this feasible? NRST is the output of the reset chip.

[waclawek.jan]

How are all VDD/VSS/VDDA/VSSA/VBAT/VCAP pins connected?

JW

[Haixiang]

Thank you for your reply.

VDD is a voltage reduction from 24V to 5V, and V is reduced to 3.3V. All VDD and VSS are in a series connection. It seems that the VDDA and VSSA chips are not available. The VBAT is disconnected. The VCAP is grounded through a 2.2μF capacitor.

[Haixiang]

Do you think it might be interference caused by the power supply? The 3V3 ground and the 24V ground are connected in series.