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STM32H503 I3C, I3C_RSTDAA_THEN_ENTDAA issue

Hi, I am working with STM32H503RB.I'm currently testing the function of "I3C_Controller_ENTDAA_IT" from the example code.Capture1 is the result of "I3C_RSTDAA_THEN_ENTDAA"The expected behavior of Capture1 should be 7E06 then 7E07.Why would 7E02 occur...

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SteveDu by Associate II
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  • 3 replies
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STM32G030 debug in low power sleep mode

Hello,I've a project with the STM32G030F6 which the application use in 90% of time the low power sleep mode. In the reference manual page 95 is written that can debug:But in the register DBGMCU_CR dosn't exists a flag for the low power sleep mode. On...

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bm2 by Associate III
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Hard fault on Using FMC ram on stm32h753

I'm using a STM32H753 with external RAM. We were using it for LCD framebuffer. Now we are trying to migrate the stack and heap to the external RAM, when we run the code, getting hardfault on lines where std::array is declared. Any idea on how to debu...

sivaram by Associate III
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  • 11 replies
  • 2 kudos

STM32H7 CPU stall after RDP level change

I have an issue when changing the option bit of STM32H742 to change the RDP level to 1.I read out option bit from register FLASH->OPTSR_CUR, change the RDP bits to eg 0xBB, write the result to FLASH->OPTSR_PRG and then set bit FLASH_OPTCR_OPTSTART in...

Resolved! STM32Cube_FW_U0_V1.0.0 Version problem

I have recently upgraded CUBEIDE to v1.15.1I tried to add a example project to my workspace and it states Required Software PackageWhen I click next and finish, I get the errorI have checked for updates etc and tried to download manually using Embedd...

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JK_lin by Associate
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Flash corruption and write protection mechanism

Posted on March 25, 2016 at 09:45We are using STM32F405 in our product which is a controller. We have met strange problems reported by our customer but can't reproduce the phenomenon in our lab when taking the controller back from customer. The cont...

BSMX falling edge data not always available

I am working on an application using an STM32U5A5 nucleo board with four MEMs PDM output format microphones. The microphones are configured such that data is valid for the left channel on a rising clock edge and valid for the right channel on a falli...

jcmoreau by Associate II
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Resolved! Configuring STM32F439 timer to pulse at specific counts.

I wanted to use the STM32F439 timers, any of them but timer 8 seems to be the best one with my current peripherals, to act as a trigger source. Basically, the timer would drive a pin low, and at specific counts of the timer, drive the pin high for ~5...

EBDRS by Associate II
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  • 11 replies
  • 2 kudos