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Posted on April 13, 2016 at 17:00Has anyone ever had any problems with the amplitude of a clock signal when using an external crystal in HSE mode?I have a board that I built that oscillates reliably and accurately, but the amplitude of the signal is...
Posted on January 26, 2016 at 03:52Hello All, I am having trouble using the USB OTG peripheral on the 32L476GDISCOVERY board. I took off the LCD and shorted the solder bridges that connect the Vbus (and the USB ID) pin. I am trying to use the bo...
Posted on March 28, 2016 at 23:46I am trying to use the CMSIS interface to FreeRTOS that is generated by the Cube application. Specifically, I am trying to use the osSignalWait, osSignalSet, and osSignalClear functions. Problem 1: osSignalClear is ...
Posted on April 13, 2016 at 12:38 The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on April 13, 2016 at 06:16I have an ADC1 buffer that is being filled by DMA once every time on this call:HAL_ADC_Start_DMA( &hadc1, (uint32_t *)ADC_Data, 3 ); Where: uint16_t ADC_Data[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF }; I can tell by th...
Posted on April 11, 2016 at 22:31CubeMX thinks there is a ''FW.L1.1.1.5.0'' update for the STM32L1 parts.However, it cannot download the update (''Not yet available'').When I download manually from the website, it seems like the cube software is onl...
Posted on April 06, 2016 at 15:47Something was changed in the last couple of days. It comes up with an XML pane, and a pop-up complaining. ''Web.config registration missing! The Telerik dialogs require a HttpHandler registration in the web.config f...
Posted on April 12, 2016 at 21:15Hi.First, I would like to ask about page erase time. As stated in RM (for STM32F303) it should last min. 20 ms to max. 40 ms. But I checked it with ETM profiler and the whole process of erase took only around 100 us....
Posted on April 12, 2016 at 21:40Is it possible to connect the SAI MCLK signal such that it can be used as a clock into a timer which is counted down to provide an ADC trigger - or are there aliasing issues with the timer? I want an internal ADC to ...
Posted on April 12, 2016 at 17:44In my understanding, DTCM, SRAM1 and SRAM2 all offer single cycle access. This leads my to the conclusion, that enabling DCACHE in a situation where there is no slow external memory does not bring any advantage, but ...
