STM32 MCUs Products

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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! STM32L432 - I2C Address Off By 1-Bit

Posted on February 24, 2017 at 06:55 Hi, I recently brought up the I2C using the STM32CubeMx(4.0) and STM32CUBE_FW_L4_v1.6.0 and I was attempting to write to a slave device with an address of 0x2A. I noticed that my slave device was NACK-in...

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Nolan L by Associate III
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How to set stm32f407 sdio to 48Mhz?

Posted on February 25, 2017 at 17:25hi i want use sdio as 8bit mode and 48Mhz but i try to do this and i saw max 25Mhz on clk line for sdio port.how can i set sdio as 8bit-48Mhz mode?tnx for replay

eittinfo by Associate II
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I couldnot make STM32F103RC CANBUS work

Posted on February 24, 2017 at 17:37hello dear forum,I copied following code from std peripheral libraryhowever I couldnot make it workwhat I am doing wrong ?thank you----------------RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);--------------...

Resolved! STM32F3 UART DMA problem

Posted on January 04, 2017 at 00:01 Hi,I am working  on an application on an STM32F303RET6 on a nucleo board. I am struggling to get DMA working on USART1 Rx.  I can successfully enable the USART port and it works correctly with the receive interrup...

STM3221G-EVAL and SSD1963

Posted on December 04, 2014 at 20:09Hi:I am using the STM3221G-EVAL board and trying to use a a different TFT display than the original that came with the board. The original display is an Ampire display that uses a Ilitek controller ILI9320.The new...

eduardo2 by Associate II
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STM32F4 ADC w/ DMA application notes & examples

Posted on February 24, 2017 at 17:09We are using the STM32F437 and I am trying to find application notes for using ADC with DMA. More particularly I would like to see notes or code examples where multiple channels (2) are interleaved. Thanks,jh

John Hite by Associate III
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