['F446 documentation] RCC - using odd output dividers on PLLs
Posted on January 18, 2018 at 00:18Some PLL/PLLI2S/PLLSAI outputs (namely R and Q) allow odd dividers, which results in assymetric clock waveform (the extreme is divider=3, with duty cycle 2:1). The Q output of PLLI2S and PLLSAI further goes through...