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Hi.I have Uart pins (Rx/Tx) PA3 and PA2 on STM32F407VET6. Can these pins be changed to I2C (SDA SCL) in the program?Are the pins on STM32 that have been assigned a protocol (SPI/I2C/Uart) constant and cannot be changed or replaced?Thank you.
The maximum I2C (Standard) Rise Time/Fall Time of STM32F413VGT is stated as 0.1us/0.3us, but STM32 Datasheet says 1us/3us. Please confirm which one is correct.
MCU: STM32F767ZI-NUCLEOSTM32CubeIDE Version 1.19.0Hello Everyone!We are trying to make the MCU enter DFU mode through firmware (without connecting BOOT0 and VDD). DFU mode works well, but we do not know how to determine USBD_DFU_APP_DEFAULT_ADD and U...
Hi fellows,I have a custom board with STM32F407VGT6. The board was able to be programmed via the JTAG (4 wire JTAG interface; Boot pin is pulled low to ground and reset is connected to the JTAG interface (Nrset pin)) with a segger programmer - multip...
Hello,I have application which go to STOP2 mode once no LPUART/Modbus communication (Running at 32Khz LSI clock) is in progress.Using lptimer for silence timeout logic for UART data frame completion. The code sometimes cause delay during modbus commu...
Hi All,I am trying to send data to SPI1 via DMA1 Stream 0, using a timer to trigger DMA.Currently, I have used TIM4 Channel2 and Enabled DMA Update with DIER register (UDE bit).DMAMUX1 Channel 0 Request is set to 32.So far, this part seems to work: I...
Hello, i am stuck on UART topic and i have an argument with someone.He states that ReadMemory(0x11) is sent by STM32. Is that really so? Does STM32 at any point sends "0x11" as response? I must be missing something...
Hi in an dual core stm32h7, if we use each iwdg for each cores, when iwdg trigger reset,it will reset the particular core or both the cores will reset.If particular core reset happens means, how to manage the other core from initial boot.Suppose if c...
MCU: STM32H723VET6ADC: ADC1 / ADC2 / ADC3 (12-bit, single-ended)VREF: 3.3 VApplication: Digital Multi meter (DC / AC voltage measurement) Problem DescriptionIn my DMM hardware design, the Analog frontend applies a mid-scale level shift (VREF/2 = 1.65...
I have a custom board with an STM32G051. The STM32 is a SPI receive only device. PA1 is SCLK, PA2 is MOSI, PB0 is nSS (which is hardware controlled). The beginnings of the project where created with CubeMX so the clocks should all be set correctly...
