phase shift HRTIM between Tim1
I wanted to generate without Phase shifted PWMs between HRTIM and Tim1 .How can I do it? thanks for your support!
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I wanted to generate without Phase shifted PWMs between HRTIM and Tim1 .How can I do it? thanks for your support!
Hi everyone,we are moving our design from usb full speed to usb high speed using STM32F76VI.We want to use the suggested module STULPI01A in order to achieve this.On datasheet is specified to use a precise reference clock.Since our application use a ...
Hi everyone,I'm working with an STM32U5 and using USBX with the CDC-ACM class.My setup is as follows:I have a USBX CDC ACM receive thread that calls usbx_cdc_acm_read_thread_entry() in ux_device_cdc_acm.c file.Alongside, I have a state machine runnin...
Hi,While working on the code for an STM32H7B0, I'm having issues with the blanking function of COMP1. Specifically, it works correctly when the comparator is in non-inverting mode, but if I invert the comparator's output (to detect falling thresholds...
Hi, SPI CR2 is missing from RM (RM0383 Rev 3) table in 20.5.10 SPI register map (page 610). Please update. Best,Alessandro
Sorry if this is extremely basic, as part of our program we had to install(?) RTOS on our boards to do some of the labs, but we had to reinstall ST-Link after. Now the board refuses to debug. I'm getting these logs:xPack Open On-Chip Debugger 0.12.0+...
Hello,I have two questions regarding the STM32U0 series and the RM0503 reference manual:1/ HSISYS Divider ConfigurationIn RM0503, for the STM32U0 series, it is stated that HSISYS is a clock derived from HSI16 after division by a value from 1 to 128.T...
Trying to get MD5 hash acceleration working on the Nucleo-H563Zi. I can get SHA1 hash engine to work via bootstrapping a project via CubeMX, but for some reason MD5 is not a selectable option for the hashing algorithm in CubeMX. All other algorithms...
Hi , I am also making custom board for GPS, and same issue I am facing, unable to connect via SWD, Please help to debug.
The DBATTEN setting in the UCPD_CR register claims the following But as far as I know, the dead battery functionality is always present. It would have to be to work unless this is stored in NVM.Maybe this DBATTEN is some other Rd value? Maybe the ANA...