Ask questions, find answers, and share insights on STM32 products and their technical features.
RM0433 Rev 5 writes:The recommended single write sequence in bank 1/2 is the following:1. Unlock the FLASH_CR1/2 register, as described in Section 3.5.1: FLASH configuration protection (only if register is not already unlocked).2. Enable write oper...
Hey guysI'm currently wondering why i'm not reveiving any interrupts at all on my STM32F413I used cube mx to create a new project.For starters I'd like to send some data via UART with an interupt transfer.uint8_t dummy[4] = { 0 }; volatile HAL_Status...
The project is using MCU stm32f103C8T6 for controlling. Here we use the peripheral ADC for current sampling, and we need the time from the interrupt happening to the interrupt executing less than 2us. But the codes following spending about 6us. How...
Hi guys,I’m new with x-cube sbsfu package and I have some troubles with running the example on stm32l476. I saw the stm manual for getting started etc but it didn’t work for me. Can anyone explain how to import properly project into workspace in Atol...
According to what documentation I can find, ECC is supported in the caches, the TCMs, the system SRAMs, and the Flash.For caches, the situation is simple: caches must be invalidated before being enabled (whether or not ECC is present), and the Corte...
Hello,i am trying to figure out how to read out the ECC Status for the L1-Cache of a STM32H743 Microcontroller. I managed to find out how to enable or disable ECC in the instruction and data Cache but I cannot find the place from where to read out a...
I am using STM32L4R5 and S25FL128L (quadspi) NOR flash interfaced over OCTOSPI. Currently we are using single channel for erase, read and write operations. Read and erase operations seems working fine. But we are facing issue for write/program operat...
I have some problem about this issue, i try a lot of to fix it, but it can not run like i expected.If all words i post make anybody difficulty understand , i so sorry a lot.My problem is:Fisrt , i enable interrupt USART_IT_RXNE,Second, in my ISR, i c...
I have an application, which uses 2 channels of TIM1 to drive a full bridge d-class power stage in order to generate a sinusoidal signal. FSW is 200kHz. The CCR1 and CCR2 registers of TIM1 have to be updated at sampling frequency, so I am using TIM8 ...
Hi, apologies for the slightly long post, I'm hoping someone could hopefully point me in the right direction here. I'm trying to perform the FFT of a 100Khz signal using the STM32 Discovery board but I'm relatively new to the STM32 DSP in general. I...
