STM32 MCUs Products

Ask questions, find answers, and share insights on STM32 products and their technical features.

cancel
Showing results for 
Search instead for 
Did you mean: 

Forum Posts

Resolved! STM32u5g9 usb support

Hello, I have been trying to implement USB support on an STM32u5g9vjt6Q using USBX in standalone mode without success as of yet. I have been referencing this guide (How to implement USBX in standalone mode ) I am trying to use the onboard USB Phy in ...

Screenshot_20250601_160300.png
brohr01 by Associate III
  • 127 Views
  • 2 replies
  • 0 kudos

STM32H753VIT6-external crystal issue

Hi,  IM USING EXTERNAL CRYSTAL NX2016SA-25M-STD-CZS-1 IN HSE 25MHZ AND LOAD CAPACITOR 10pF ,BUT I'm TRY TO USE EXTERNAL CRYSTAL IT CAN'T ENABLE . LSE 32.768kHZ ALSO NOT WORK ,HOW TO ENABLE THIS EXTERNAL CRYSTALS .MY CONTROLLER PARTNUMER IS STM32H753V...

STM32H503 code execution performance issue

Hellofor some specific usage I am evaluating possibilities of using CM33 with HCLK 250MHz for maximum code execution performance. To do so I have crafted procedure in assembler and calculated the cycles using ARM reference manual. The code is doing o...

ULPEN - ST please unify nomenclature

In 'G0B1, 'G071 and 'L412 Datasheets, ULPEN is mentioned several times (namely 3 times).It probably corresponds to PWR_CR3.ENB_ULP in case of 'G0x and PWR_CR3.ENULP in case of 'L412/'L422.I did not check if this propagates to newer STM32, too.ST, can...

Square wave FSK issue using PWM ouput

Hi All,I am trying to impliment a frequency shift keying (FSK) routine to represent a each bit of a byte as FSK.My routine is kind of working (see the IRQ for TIM3 below). My FSK is :Bit 0 & Start : 3600Hz Bit 1 & Stop : 1200HzThis ensures that timin...

Screenshot 2025-05-30 124318.jpg

Resolved! Capacitor for VREF pin on SMT32L4P5CG MCU

Hi, I´m beginner in SMT32 MCU design, I´m doing a design for the above MCU and in the document "AN4555" that is for hardware develoment of these MCU series I founf that So for my package (64 pins) the VREF and the VDDA power signals are bounded insid...

Aldo_Flores_Aguayo_0-1748633646547.png