About Michal Dudka

Michal Dudka · 2025-01-28

Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at in...

Michal Dudka · 2025-01-27

Hi,I am using PSSI on STM32H7R3 to transmit data with DE output signal and RDY input signal (flow control). Incoming clock frequency is 60MHz. Data buffer is located in AHBSRAM1 and have size 4096 bytes. GPDMA feeds PSSI buffer by 32bit access (four ...

Michal Dudka · 2025-01-23

Hi,STM32H533 datasheet (DS14539 Rev 2) in table 88 says that RDY input setup and hold time are both 0.5ns. From my naive point of view it looks like superb value (RDY have to be stable only +-0.5ns around CLK edge). Isn't that a typo ? (STM32H7 PSSIs...

Michal Dudka · 2025-01-23

Hi,Ref.manual (RM0477 Rev 8) in chapter 32.3.3 PSSI clock saysIn case when PSSI transmitting data, then RDY pin is input.Datasheet (DS14360 Rev 2) shows setup and hold time of RDY pin (input) referenced to rising edge as well as data pins (outputs).I...

Michal Dudka · 2024-10-17

Missing info about PG12,PG13, PG14, PG15 alternate functions in Table 22 (datasheet DS14359 Rev 2). I hope that PG15 AF9 is PSSI_D13 like PG11.

Michal Dudka · 2025-02-06

I've tested 8bit width 60MHz on STM32H7R3 (Fcpu=600MHz) from AHB-SRAM1 using GPDMA (transfered by 32bit words). The result was a completely smooth transmission without gaps.

Michal Dudka · 2025-02-05

Don't you want to take a look at it? The procedure is simple and the consequences are crucial. In every situation when the receiver delays (using RDY) the transmission one or two clocks before the transmitter "planned" to delay the transmission itsel...

Michal Dudka · 2025-02-03

Hi @KDJEM.1 I'm glad to hear that it will be fixed. What about this, much more serious, issue ?https://community.st.com/t5/stm32-mcus-products/stm32h7r3-pssi-rdy-de-bug/td-p/766737PSSI obviously transmit data even with deasserted DE signal under well...

Michal Dudka · 2025-01-28

BTW: What about to use capacitor to supply MCU during startup ? For example 220uF capacitor drops from 3.3V to 3.0V after 50ms if source current 1mA. And can be charged from 0V to 3.3V in less then two seconds.

Michal Dudka · 2025-01-28

I had no choice but to test it. I've generated 16MHz clock from lab generator as source for CLK input. On second channel i've generated 20ns pulze connected to RDY input. Then i've changed RDY pulse phase shift respect to CLK to check if RDY is read ...

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