IWDG PVU bit is not being reseted by hardware - STM32F103C8T6

[EveG]

Hi,
I'm configuring the independent watchdog in the STM32F103xx medium-density using the registers.
During the IWDG the PVU bit is not cleared by the hardware. The reference manual (page 498)  says the following:

"PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to 5 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset."

	RCC->CSR |= (0x1 << 0); // Enable LSI
	while (!(RCC->CSR & (0x1 << 1))); // Wait for the LSI to be ready
	
	IWDG->KR = 0x5555; // unlock PR and RLR

	IWDG->PR = 0x3;    // Divided by 32
	IWDG->RLR = 0xFFF; // 4096 - counter value
	
	while (IWDG->SR & (1 << 0)); // PVU  <- #### GET TRAPPED IN HERE ####
	while (IWDG->SR & (1 << 1)); // RVU

	IWDG->KR = 0xAAAA; // reload the counter
	IWDG->KR = 0xCCCC; // start IWDG

Debugging using GDB, the RCC bits are correct, LSI is activated and being used, the 0xFFF value in IWDG->RLR is set, but the prescaler value (0x3) in IWDG->PR is not being set because the PVU bit is not being reseted.

[TDK]

It may need started before the registers are updated. That's what HAL does.

stm32f1xx-hal-driver/Src/stm32f1xx_hal_iwdg.c at 18074e3e5ecad0b380a5cf5a9131fe4b5ed1b2b7 · STMicroelectronics/stm32f1xx-hal-driver