A question about this sentence of STM32H7 reference manual:
Receive-only mode: COMM[1:0]=10
In master mode, the MOSI output is disabled and may be used as GPIO. The clock
signal is generated continuously as long as the SPI is enabled and the CSTART bit in
the SPI_CR1 register is set. The clock is stopped either by SW explicitly requesting this
by setting the CSUSP bit in the SPI_CR1 register or automatically when the RxFIFO is
full, when the MASRX bit in the SPI_CR1 is set.
In my implementation (SPI Simplex in master mode), the reception phase is controled by the TSIZE paramater in SPI_CR2 (the SPI is also disabled at the end of the transmission phase but only to cope with the SPI simplex errata of STM32H7)
But the reference manual seems to state that one should use CSUSP bit ?
Do you confirm that I should NOT control the duration of reception phase in Master simplex mode with TSIZE parameter ?
