reg addr's for GTZC_TZSC_MPCWMxANSR GTZC_TZSC_MPCWMxBNSR
The doc and SVD file don't have a reg at offset 0x44 (GTZC_TZSC_MPCWM3BNSR).Since GTZC_TZSC_MPCWM3ANSR @0x40 exists, via symmetry I would expect B also at 0x44.The doc does say this:GTZC_TZSC external memory x non-secure watermark register 1(GTZC_TZS...