DS13565 Rev 2 says under 3.20: "The embedded USB controller cannot be used on STM32G0B0KE as this device does not provide an HSE oscillator input.". Well, sounds reasonable. But same DS says in Table 11 for Pin 2 (LQFP32) PC14: "OSC32_IN, OSC_IN" whe...
RM0444 rev. 5, sec. 29.3.4 and RM0490 rev. 3, sec. 21.3.4 both employ only WDGTB[1:0], but WWDG_CFR description mentions WDGTB[2:0] with eight different prescaler settings. So actually two or three bits?
What's the difference between "LQFP32" and "LQFP 32 7x7x1.4mm"? Probably they both refer to the very same package?. A similar discrepancy appears for a lot of other packages, too. (For WLCSP it's a different matter.)
The zip-archive en.st-stm32cubeide_1.9.0_12015_20220302_0855_amd64.rpm_bundle.sh_v1.9.0.zip is apparently broken: "inflating: st-stm32cubeide_1.9.0_12015_20220302_0855_amd64.rpm_bundle.sh bad CRC dd12447e (should be c287de8a)"
By "porting the application to CubeMX" you probably mean that you picked the startup code from CubeMX, too?The startup code supplied by CubeMX initializes stack pointer, initalizes data and bss segments (probably all uncritical), calls SystemInit and...
Indeed that seems to be the case for various devices, even when the corresponding hardware in physically present but not available due to bonding/packaging, see e.g.https://community.st.com/t5/stm32-mcus-products/rm0455-stm32h7a-b-reset-state-of-sysc...
As I wanted to have CRC at very end of flash, too, I did the following: In ld script:/* CRC32 checksum goes into FLASH at the very end */.chcksm ORIGIN(FLASH) + LENGTH(FLASH) - 4 :{. = ALIGN(4);KEEP(*(.chcksm)). = ALIGN(4);} >FLASHI.e. no extra memo...
"... attempting to write some optional bytes." is rather vague. Apparently some PCROP and WRP area settings had been touched. Probably the only way back is reset WRP areas to default (see "ST production value" in RM), set PCROP_RDP bit and do a RDP r...
If you want/need to stick with TSSOP-20:Most STM32 devices allow trimming of HSI, so if you have a spare timer and enough flash left, an option might be to use a 32.768 kHz crystal for LSE and trim HSI periodically based on LSE, see AN5857 (that's fo...
