I am designing with an STM32H745. I need to use the FMC bus to access my own ASIC. What is the full cycle time on the FMC access if I do back to back single read or single write with multiplexed address/data.
The access time of the FMC is not the whole equation, I need to include the delays introduced by having to go across domains and buses. Back to back reads or writes would shine more light on this for me. Or possibly a read followed by write so that ...