Resolved! Refresh IWDG before initializing it , result in Flash PGSERR
I looked at reference manual and didn't see what was causing this.
Forum Posts
How to send and receive simultaneously with USART using HAL?
Hi, i did some research and when i do send and receive seperately then everything went smoothly, im using HAL_UART_Receive with RxCpltCallback: if(huart->Instance == USART2 && newDataFromPC == 0) { /*Receive data*/ HAL_UART_Receive_IT(&huart...
STM32H753 writing to Flash
Hi , i am using STM32H753 MCU, it has 2 banks of 8 sector each using HAL_FLASH_PROGRAM function , it is not working, can anyone help me with this issue.int data;StartSectorAddress = 0x080E0000eg:(HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, StartSe...
data retention
i am using stm32h743zt6 controller, what is meant by data retention in flash memory?where this parameter?how we can calculate this?Thanks,
SPI1 DMA hardware nSS control for use with Wiznet W5500 network chip.
Good day everyone.I'm trying to get Wiznet made W5500 working with STM32F030 series, using SPI in DMA mode.Unfortunately, in nSS hardware output mode, SPI bus pulls up nSS line after every transmitted byte (see attached image), while W5500 manual sta...
Hi, I am new to the STM32. The function SystemCoreClockUpdate() in the library file system_stm32f10x.c extracts the PLL multipl. factor PLLMUL[3:0] from the RCC_CFGR register. Question: why the '+2' here: pllmull = ( pllmull >> 18) + 2;
void SystemCoreClockUpdate (void){ uint32_t tmp = 0, pllmull = 0, pllsource = 0; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system...
Why is my 512 Hz RTC_OUT_CALIB signal "much" less accurate than the 1 Hz signal?
Trying to generate a 512 Hz signal that is synchronous to the LSE.MCU is an STM32L476ZETx.Measuring the signal on RTC_OUT_CALIB with a Keysight tabletop multimeter. (And also with an oscilloscope.)Observation:Setting "RTC_CALIBOUTPUT_1HZ": measured f...
I wondering if anyone out there has experienced LSE clock seeming to run fast?
We're using a STM32L4a6 with an ABRACON 32.768KHz crystal (ABS06-127 which is on listed in AN2867 as a compatible crystal) however we seem to be observing error in to order of +200ppm (not the +/-20ppm given in the crystal specs). Using 1p2F caps an...
SPI read is getting right shifted 1 bit of every byte in STM32L476ZGT6 at 20MHZ SPI CLK(SCLK)?
I am working on STM32L476ZGT6 EVAL-Board for transferring data on the SPI to one of the audio codec which is SPI slave. I am trying to read the data from codec at 20 MHz SCLK. I am seeing that the data is getting right shifed 1 bit for of every byte....
