Tim malfunction problem when iwdg is active
I was coding with nucleo f401re board in stm32cubeide. However, I found a problem with timer not working properly when iwdg is enabled in ioc settings. Do you know a solution to this?
Forum Posts
STM32407x ADC , DMA and overrun
Hello, I want to know when ADC DMA is enabled and if ADC overrun status sets to 1. the RM says this >>>>>>>>>>>>>>>>.To recover the ADC from OVR state when the DMA is used, follow the steps below: 1. Reinitialize the DMA (adjust destination address ...
How to migrate a project built on STM32F0 platform using Standard Peripheral Library to STM32G0?
I had built a project using the device STM32F030C8T6 with the help of Standard Peripheral Libraries (SPL). However, I would like to migrate to the newer series of STM32G0, using the device STM32G030C8T6. But, I found that there are no SPL libraries f...
High start up time for STM32L4
I'm currently developing a project that will see a high number of MCUs connected in the end application so low power consumption is critical. I was aware there will be some initial high power consumption when first powered up however the MCU takes ~3...
I think I am in the wrong place
can anybody tell me how to get in the Black Pill fourum ?
FSMC_NOE and FSMC_NWE confliction with FSMC external NOR/SRAM read operation
Hi Team,STM32F407 running on STM32F4xx_DSP_StdPeriph_Lib_V1.8.0 with the following init configuration,void USBFIFO_FSMCConfig(void){ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; FSMC_NORSRAMTimingInitTypeDef p; p.FSMC_AddressSetupTime = 0X00;/...
Hello, I have been working with a STM32F4 where I use two channels of TIM8 to trigger data transfers from two GPIO ports to memory using two DMA2 streams. I would like to have these DMA streams write 16-bit data interleaved to 32-bit memory addresses.
I have gotten the 16-bit data transfers individually working where each DMA stream would write to memory in half-world fashion. For this application it would make more sense to write 16-bit data from GPIO port I to the lower half of a 32-bit word and...
STM32 QSPI Bank1 and Bank 2 usage
Hi All,We are planning to use STM's STM32H750VB in our design.We need 1 QSPI port from the MCU.We saw in the reference manual following 2 things: 1. In block diagrams (page 883) it is mentioned as if we can enable dual-flash mode (8 bits) and disable...
DMA underrun and overrun
Hello, Thanks for wonderful support I am working on STM32F407X mcu DMA program and want to understand when will DMA underrun and overrun happens. This is not explained in any of the ST documents even though the RM mentions this>>>>>>>>>When burst tra...
What is the pin overlap between the Nucleo's Morpho connectors and ZIO connectors?
I'm using the Nucleo H743ZI2 right now and have mostly just been using the pins accessible through the ZIO connectors (CN7, CN8, CN9, CN10). I'm wondering about the main purpose of the Morpho connectors (CN11 and CN12). I've noticed most of the Morph...
