Hello,I have a custom PCB with stm32L562 on it. I'm able to put it low power run mode.My consumption is 0.2mA, but if I init ADC the consumption jums to 0.3mA.I've tried to deinit it before going to stop 1 mode but it does not helpHAL_ADC_Stop(&hadc1...
in code : // Bit1 CPOL: Clock polarity // 1: CK to 1 when idle SPI2->CR1 |= 1<<1;in fact clock is Zero when idle .interrupt not work, src: // Bit 7 TXEIE: Tx buffer empty interrupt enable // 0: TXE interrupt masked // 1: TXE int...
Hi,I have tested STM32H745 CM7 SD 1bit mode with out RTOS from cube generated files (STM32Cube_FW_H7_V1.7.0) and it's work fine for FATFS file operations, as soon as by adding freeRTOS in cube, the generated files have HAL SD init and f_mount works b...
I'm using SMBus on an STM32F303. The application has the STM32 as host, SMBUS charger and SMBUS battery, the charger and STM32 can act as master.I need to infrequently read from the battery and want to check for IDLE before initiating a transfer.I've...
When I2C "Speed mode" changes in CubeMX/IDE from Standard to Fast, it seems that only the Init.Timing value changes in generated code.This value goes into TIMINGR register of the I2C .Am I missing anything or this value defines the "speed mode" entir...
I have a strange situation with my implementation that in all other cases runs smoothly, tested with baud rates up to ~250K. During an interaction with a specific peer that is instructed to reset, a framing error is detected when this peer reappears ...
For the external RTC clock of stm32f765igt6 chip, we use a 32.768KHz crystal oscillator of Epson, which is equipped with 10PF capacitor. Some of them will make the MCU unable to start, and reduce the capacitance value to 2pF, MCU can start, but we ac...
Hello,I have been testing a custom board using the STM32F767ZI/VI for the last two weeks, and most things have been going well. I ran into an issue using CAN on the VI for some reason so I decided to switch to the ZI, and things were working well unt...
Hello,both STM32L4 and G4 reference describe in LPTIM->CFGRBit 21 WAVPOL: Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registersThis...
The LPTIM erratum "MCU may remain stuck in LPTIM interrupt when clearing event flag" (to be found in errata of STM32 having LPTIM, which got updated since cca the end of 2018 -- ST please update *all* errata timely!) contains this description:This l...
