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Hello all!I am trying to play with the deep sleep mode of the stm32g031f8p6.Now i am using this: To sleep: SystemClock_Decrease(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2); HAL_PWREx_EnableLowPowerRunMode();To wake up: HAL_PW...
I have a C project on an STM32F745 that uses various HAL libraries.Today I have enabled the WWDG (Windowed Watchdog.) I set the registers directly as I find that easier to understand and did this right at the start of main() to offer best protection ...
Hi, I am trying to communicate on CAN BUS, I have previously succeeded in doing so with STM32F103C8 and STM32F091RC, but I cant make it work on STM32F407VET It does not trigger its interrupt on message receive. What could be the difference on this MC...
As we are using CAN 2.0 A (11 bit ID STANDARD FORMAT) in STM32L431RBTx MCU & it is working fine. Now we want to go for the CAN open protocol. Is there any sample code or document available or any algorithm to initiate CAN open code development for ST...
For PWM channels to be disabled during a trip instant we use the break input circuit and the function worked well in the Nucleo board. But while using the same in the real circuit having half-bridge, cross conduction occurs every time the break input...
I'm running into the Cortex M7 r0p0, r0p1 bug where single-stepping is impossible due to the processor handling an interrupt instead.i.e.http://www.keil.com/support/docs/3778.htmI'm using OpenOCD and it is reporting:Warn : Silicon bug: single steppin...
hello,Should I use TXFIFO or RXFIFO to send and receive SPI data in a continuous flow?In that case, do I have to enable CRC calculation?If you have to enable CRC calculationI don't want to send or receive CRC data.Is there any other way?Goto
If I try to configure the interface from the CubeMX tool, it seems that it is possible to communicate only with flash memories.I have a lot of data that I need to transfer from a uC to another on the same PCB and a single SPI is too slow. Are there o...
i configure tim1 bkin. after bkin is triggered, tim1 2 3 output seems like high-z state.my ossi bit is 0. MOE is cleared by trigger. according to reference i can set corresponding GPIO to high or low. but it doesn't work.
The ST self-test library(en.x-cube-classb-v2-3-0) tested both watchdogs( IWDG and WWDG). Is it necessary to test both IWDG and WWDG for class B compliance? In the self-test library, they used both watchdogs. If I use one watchdog timer let's say WWDG...
