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Resolved! usart2 stm32g030k8 does not work correctly

Hello everybody!I can't use USART2 in STM32G030K8 to transfer data.The TC flag of the ISR register is not set after writing data to the TDR register for an infinite time, if I use it to control the transfer of a byte, the program hangs without transf...

Akoli.2 by Associate III
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The DMA buffer configured with a multichannel ADC setup ( Processor STM32f769II) shows values in different buffer location with respect to the rank configured in the ADC setup. How can this be fixed?

We have connected 7 channels in ADC2 to a STM32F769II processor. The DMA to ADC is enabled and the rank for conversion too is configured. But on testing, the ADC values are being shown in buffer location very different from its rank.This happened in ...

SP.7 by Associate
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STM32L496RET6

please let us know the availability of STM32L496RET6 controller

APara by Associate II
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MCU : stm32h743ii. two usart problem

i use two uart.(usart1 & usart2).when i receive data(usart1), first, the program will into "void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)".but when i i receive data(usart2), second, the program will not into"void HAL_UART_RxCpltCallback(UA...

RLiu.11 by Associate II
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  • 3 replies
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SPI DMA fails (only) with ICache enabled, why?

I have a project which uses SPI DMA, and the SPI DMA appears to fail when I enable the instruction cache (ICache! not DCache), but otherwise appears to work perfectly fine. I do observe this for both a F722ZE and G491RE.I'm working on this since 3 we...

waldmanns by Associate II
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  • 6 replies
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STM32L4R5 not always booting after nRST

We are seeing an issue with the STM32L4R5ZI that does not boot 100% of the time if nRST is asserted after powering up (i.e., pressing and releasing reset button). We have seen this issue with the Nucleo board and with two different boards we made our...

RDowl.1 by Associate
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  • 2 replies
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