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Hi,Is there any functional block diagram programming for STM32 microcontrollers? The logical operation, input management, arithmetic operations, decision controls, etc.Regards,Umit
I have a problem when debugging STM32L4 form CubeIDE with STLINKV2, the debugger only starts every other time. First start of debug session is ok, program halts at "main()". When debug session is closed and started again, the download is successful, ...
Thats a question that has bothered me for a while. When receiving FDCAN messages, I can specify a watermark on how many bytes the interrupt triggers.How exactly does it work?If I have a message of 8 bytes and I set the watermark to 1 byte, does the i...
Hello , I am using NUCLEO-H7 board it operates on 400MHZ clock frequency the APB clock is 100MHZ.But on which frequency spi operate on 400MHZ or 100mHz. In stmcubmx clock configurationSPI 1,2,3 clock mux option selected is PER_CK 64 MHZ. And baudat...
I am trying to configure two timers (TIM3 & TIM4) to start at the same time, following the procedure in RM0440 pg. 1304. However, when I scope the output pins of my timers, there is a ~25us delay between the edges of the pulses. Is there any way to e...
Hello there,When debugging in STM32 ST-LINK Utility, there is a problem that device information is written as STM32F07x.I conducted the test with 2 types of MCU and the problematic model is STM32F401RBT.If STM32F401RET is used, it will operate normal...
Hi All,I'm using the following code to set up 4 external triggers and this all works well. What I'd like to do is to be able to change the trigger type of any of the EXTINT at some point in the program. I've tried a couple of things which only resu...
First, the "atomic" port ODR issue when more than one function or task may use the same GPIO port. Is the best thing to do ALWAYS to use BRR and/or BSRR to change the ODR values? From what I've read we need to be wary of an interrupt or other task ch...
How many clock cycles should it take to write to AXI SRAM from the M7 core, assuming that the cache is disabled (and disregarding instruction pipelining)?The reference manual says:"The system AHB SRAM can be accessed as bytes, half-words (16-bit unit...