Hi, I want to use the simulataneous ADC reading with 2 DMA channels, in order to avoid overrun errors (which I'm having).I'm using the HAL and I'm having a hard time understanding when is the DMA buffer of the slave channel assigned. When multimode i...
Hi,I am using STM32L476VGT3. When ADC1, ADC2 and ADC3 are configured independently, everything works fine. As soon as I write into the DUAL[4:0] bits of register ADC_CCR (common control register) to set ADC1 and ADC2 in dual mode, ADC3 stops. The dua...
I'm working on a project to generate composite video from an STM32 using the high speed DACs.This requires 3 DAC channels for red, green, blue fed by DMA.Of course the red/green DMA conflicts with the blue, hence the blue output is delayed about 30ns...
Currently I am just trying to share some data between cores, and right now I'm just trying to send a constant value to confirm operation.I have this code located in a file called share.h,typedef struct { // shared data goes here int16_t data; }...
Edit: It seems there's a bug that will randomly delete sysmem.c and syscalls.c.If it happens, cubeMX won't regenerate them.Also no warnings at compile time, so you won't suspect anything was deleted.So the solution is to make a new empty project and...
I use IAR to program STM32,the map file shows that :the RAM is divided to 1.data Section;2.CSTACK and HEAP section;3.bss section;4.Unassigned part of the RAM。What I want to know is that:The Unassigned part of the RAM is used to do what? Because I w...
I use tim dma burst to update CCRx(x=1\2\3\4),my code works,but the CCRx value not assigned in correct sequence. My purpose is to let CCR1= 360�?CCR2= 720�?CCR3=1080.But the result are random.TIM and DMA config codesvoid tim_config(){ uint32_t addres...