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DFSD with two PDM mics using a single input

Hi,I followed the example for DFSDM found in DM00380469_ENV1.pdf and setup the channels as specified (channel 0/1 -> input from ch1 and internal clock). Cube MX also creates 2 pins , CLK and DATAIN1.STM32F413 MCUIt seems that I cant get any data comi...

NKara.3 by Associate II
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  • 3 replies
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Cannot use CAN on alternate pins

Part is STM32L4Q5CGIf configured to use PA11 and PA12 on AF 9 works as described in programming reference. When changing pins used to PB8 and PB9 CAN cannot be used and never leaves reset. On my custom board I have PA11 and PA12 in use by USB so I ca...

DPlum by Associate II
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  • 4 replies
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Resolved! What is the meaning of multiplexed channels of ADC's in STM32L552xx or STM32L562xx family micro controllers

I stuck with ADC implementation understanding. Please help me to get this.In STM32L5xx reference manual (RM0438), ADC main features are given as follows (Page no. 685 in RM0438 Rev7)" Up to 2 ADCs which can operate in dual mode:ADC1 is connected to 1...

MSatish by Associate II
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  • 2 replies
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I2C Timing Calculation for STM32H7

I want to know how to calculate the Timing register content on my own for the I2C clock speed, I know that it can be generated by the STMCubeMX.

MFawzy by Associate III
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  • 3 replies
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STM32F105 unsigned division wrong result

Hello community,Processor : STM32F105 (Cortex M3)Compiler : GCC 6.3.1I would like to execute the following assembly instruction :udiv R3,R2,R3where :R2 = 64 000 000R3 = 1Instead of getting R3 = 64 000 000, I get R3 = 2047I tried to execute strictly t...

JPasc.2 by Associate II
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  • 2 replies
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DFSDM DMA: Which CPAR register?

Hi - I'm having trouble getting DFSDM input to work with DMA - I'm unable to set the `DMAEN` bit in the DFSDM register.One troubleshooting angle: What register pointer to you pass to the DMA's CPAR? I assume `DFSDM_ FLTxRDATAR` for regular (non-injec...

DOCon.1 by Senior
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STM32F105 Multichannel DMA ADC Read Buffer Offset Error

MCU: STM32F105RCTxFirmware Version: STM32Cube FW_F1 V1.8.0I have DMA setup to read 8 channels of the ADC into a fixed buffer and I'm having an issue where after an extended period of time (usually hours) the ADC channels are read into the wrong buffe...

0693W00000FBEl8QAH.png 0693W00000FBElNQAX.png 0693W00000FBEmGQAX.png 0693W00000FBEmLQAX.png
Jon Enz by Associate III
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