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LIORI.1
LIORI.1
Associate
June 23, 2020
Solved

Need a clarification on NRST_MODE functionality

  • June 23, 2020
  • 3 replies
  • 3383 views

I'm using a STM32G031J6 MCU in my project and i need to use the reset pin as a GPIO. From what i read on the reference manual this can be done by setting the NRST_MODE option bit to 2 (GPIO). However the issue i'm facing is that if the reset pin is held LOW when the MCU is powered up it still function as a reset pin regardless of NRST_MODE setting and prevent the MCU from running my program. So my guess is that even if the NRST_MODE is set to GPIO it is not effective right on power up but instead the mode is "set" somewhere in the booting process. I cannot find any information on how much time passes between the MCU power up and the moment when reset pin is set to GPIO, if anybody have some more infos I would be very thankful.

Best regards, Lorenzo

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Best answer by Peter BENSCH

Please have a look into RM0444, section 5.1.2 System Reset. For the mode GPIO you have selected, you'll find:

In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available. Reset is only possible from device internal reset sources and it is not

propagated to the pin.

Below the image you'l find some additional statement:

Upon power reset or wakeup from shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of trstempo.

Unfortunately trstempo is a typo and should be read as trsttempo, the value of which can be found in the datasheet at 5.3.3.and is given as 250µs (typ), 400µs (max).

Does it answer your question?

/Peter

3 replies

Peter BENSCH
Peter BENSCHBest answer
ST Technical Moderator
June 24, 2020

Please have a look into RM0444, section 5.1.2 System Reset. For the mode GPIO you have selected, you'll find:

In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available. Reset is only possible from device internal reset sources and it is not

propagated to the pin.

Below the image you'l find some additional statement:

Upon power reset or wakeup from shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of trstempo.

Unfortunately trstempo is a typo and should be read as trsttempo, the value of which can be found in the datasheet at 5.3.3.and is given as 250µs (typ), 400µs (max).

Does it answer your question?

/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
KJeps.3
KJeps.3
Associate II
August 4, 2021

Hi,

I do struggle with some of the same thing....

I have set the reset mode to GPIO in options byte - but when the pin is kept low externally, i can not connect SWD :(

Error in initializing ST-LINK device.

Reason: Target held under reset.

As soon the pin is left floating the SWD connects fine...

LIORI.1
LIORI.1Author
Associate
August 4, 2021

Hello, as Peter stated in his reply even if you set the NRST pin as GPIO in the option bytes there is a small time gap from the moment you power up the processor and the moment it reads the option bytes. Keeping the NRST pin low during that time​ results in the processor not booting at all until you stop keeping the NRST pin low. The time gap is around 250 microseconds (maximum 400 microseconds).

My solution to the problem was to introduce a RC circuit together with a comparator in order to keep 3.3V on the NRST pin for exactly 500 microseconds. This allows the processor to load the option bytes properly.

Best regards, Lorenzo​

KJeps.3
KJeps.3
Associate II
August 4, 2021

Hi,

Thank you for the answer - it may make sense...

I was just reading it different:

Upon power reset or wakeup from shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of trstempo.

To me it says: After reset the uC holds the reset pin low until it is reconfigured after trstempo...

(So it is held reset until it is configured..)

So i do not get that text to fit your explanation.... but it may be right the NRST pin is sampled in that time...

/Kasper

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