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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Quectel M66 with STM32L476RG

Hi,Hope everybody is doing great !I am trying to have quectel M66 2G modem running along with our application running on L476RG. I found the celluar package from ST for B96 modem and could integrate it to our application and it has all the features w...

ANaga.2 by Associate II
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STML011 temperature sensor accuracy

Hi,I am having problems measuring accurate temperatures with the internal temperature sensor of the STM32L011D4P7 over the full device temperature range of -40 °C to 130 °C.What I did: Measuring the temperature as described in the Reference Manual (R...

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Jens_ by Associate II
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How to implement RFU/OTA to STM32L496?

Hello,So I want to add RFU or OTA to my code as a feature. I saw an rfu source code to one of the expansion of STM32, however it is disabled. I tried to enable it by defining RFU but somehow there are missing files such as se_def.h and se_interface.h...

AMCL by Associate
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unable to debugg Hardfault error on STM32F412ZG

Hello community,I am trying to write time critical code which involves an STM32f412ZG Nucleo 144 board and a RPi communicating over SPI protocol. I have an IMU sensor communicating to STM32 board via I2C interface. I have 3 tasks, which function as ...

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AVK.1 by Associate
  • 375 Views
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IWDG and CPU Registers

I am working on STM32H7 (Cortex-M7) and using IWDG for monitoring. I am wondering if there is a way to record Cortex-M7 CPU registers (General Purpose (Rx), SP, LR and PC) when IWDG runs out. Either before or after the reset.I understand the RCC regi...

Joyabb by Associate II
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  • 1 replies
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Resolved! How to control STM32H7 QSPI Chip Select?

Hi,I am working on interfacing IS25LP128 128Mbit QSPI Flash with STM32H743 Nucleo board. I am running into problem with how the QSPI controller is driving the NCS line. The flash requires that the chip select remains low between command and data read...

Joyabb by Associate II
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  • 3 replies
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