STM32 MCUs Products

How to connect 2 input signal to any ADC in STM32H747I-DISCO board

I the UM211 User Manual of STM32H747I-DISCO board the CN9.1 (A0) is declared to ADC3_IN5 (Channel 5 of ADC3). I tried to configure ADC3_IN5 with STM32CubeMX but it configures ADC3_IN5 to PF3 (not PF7) pin. PF3 pin is not accessible in CN9 connector. ...

UART timeout in DMA Circular mode.

Hi, I have a question about UART + DMA.I have a sensor that needs to send data to my STM32. When the sensor is stimulated, for the duration of the event, it sends a byte approximately every 1 ms.To receive the data there are no problems, I used DMA a...

STM32H755 Rev. V RDP Error when erasing flash sectors

Hi there, Our application has a firmware update method that begins by erasing flash bank 2 sector by sector before writing the new firmware.RDP level is set to 0, but this shouldn't be an issue as we're only erasing a sector.Occasionally (Maybe 1 in ...

Strange behavior of IDE SW4STM32 in Code Editing and Debugging

I am using SW4STM32 (an Eclipse Variant) to code and debug my firmware, which is based on sample codes in package STM32Cube_FW_F4_V1.26.0.I have observed two strange issue:IDE warns me that "Symbol '***' could not be resolved". However, it has no pro...

Weird LPUART interrupt behaviour

Hi,i write code in bare metal so every time i initialize a project in STM32CubeIDE i do it as an empty project. I made a project for STM32L011K4 and try to initialize the LPUART, in the startup file i can find that the handler for the LPUART1 name i...

I am currently working with an STM32H747XIH6-DISCO and am stuck on how to get my DMA to trigger from an external clock source. I was going to set up a periodic DMA from a timer, but I'd like that timer driven by a 10-ish Mhz external clock. How could I?

DMB() in atomic_fetch_add leads to hard fault if MPU AXI is not cacheable

Hi there,I have got an STM32H7B0 processor.I would like to make a part of the AXI (main RAM of application) not cacheable so I don't need SCB_CleanDCache() before/after DMA write/read transaction.But another part of the AXI RAM should be cacheable an...

How to calculate minimum sampling time for ADC channels using RAIN, CAIN, RADC, CADC hardware value on STM32H7 MCUs ?