Resolved! Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?
Interface of STM32L476RG to TI CC1200 SPI. Using MCU registers with NSS produces short acceptable CSN to clock start interval but I cannot get rid of the high pulse between frames which causes the CC1200 to malfunction. Manually configuring and toggl...