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Let's assume we have a software that uses FDCAN Classic and I2C with multiple slaves. FDCAN Priority = 1I2C Priority = 2During the transmission / Receiving process, the I2C is locked : __HAL_LOCK(hi2c);If an FDCAN interruption arrives during the I2C ...
Bus speed - 100kbit/s in CAN 2.0 modeFDCAN clk - 48MhzPrescaler - 24 (bit length 20tq)TQ1 - 15 (sample point 80%)TQ2 - 4SJW - 4Receiving CAN messages without any problems, bus seems to be ok, even if FDCAN in normal mode(error counters are 0). But if...
Hello, I have been working with STM32H7 microcontrollers for a while now but have always used the single core. Now I want to use the Dual core to read and write data in the external SDRAM. I have looked through all materials available online but c...
That is what I send for exsample:SIR 9 TDI (0);SDR 334 TDI (49000000001249240a49249248000000000001249200000000000249249249008000000001249200) SMASK (3fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) TDO (0) MASK (0...
Code://LED//Pin:C//Pin Num:13#define PERIPH_BASE (0x40000000UL)#define APB2_OFFSET (0x00010000UL)#define APB2BASEADD (PERIPH_BASE + APB2_OFFSET)#define GPIOC_OFFSET (0x1000UL)#define GPIOC_BASE (APB2BASEADD+GPIOC_OFFSET)#define AHB_OFFSET (0x18000UL)...
Give me a suggestion, Is it possible or not.
On the STM32L051x6 datasheet it is written "PB9/12/13/14/15, PH0/1 and PC13 GPIOs should be configured as output and driven Low, even if they are not available onthis package" but in the "notes" space of the pin register descrpition there is no refer...
Currently we are using STM32G473CC controller for one our project, where we using CAN module(CAN 2.0 mode) in operation along with peripheral like UART1/LPUART1 in operation.We integrated CAN open stack on top of CAN driver for communication and in o...
Surprisingly, google doesn't find anything.I found the 100QFP pinout appears identical, so such a change, with no PCB change, appears possible.But it would take many hours just to compare the 300 page data sheets, let alone compare the RMs.
I've configured IWDG for my application (STM32L053). When I've halted the application during debugging, the IWDG is still triggering resets. I'm using a SEGGER j-link. I've attempted to use the __HAL_DBGMCU_FREEZE_IWDG() macro, but it doesn't seem...
