DMB() in atomic_fetch_add leads to hard fault if MPU AXI is not cacheable
Hi there,I have got an STM32H7B0 processor.I would like to make a part of the AXI (main RAM of application) not cacheable so I don't need SCB_CleanDCache() before/after DMA write/read transaction.But another part of the AXI RAM should be cacheable an...