STM32 MCUs products

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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...


How to configure HRTIM in Up-Down Counting Mode

I am using STM32 G474RE with STM32CubeIDE 1.6.1 with HAL configurations. I would like to use HRTIM1: Timer A with TA1 and TA2 enabled. My goal is to control TA1 PWM on the Up counting of Center Aligned counting (up-down counting), and control TA2 PWM...

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CWatt.1 by Associate
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Uploading to target devkit error. I have 2 x STM32F769 Discovery Kit. in 1 kit it's always running without any problem. in another kit most of the time I'm getting this error while uploading.

Run Target  Generate    Done  Generate Assets    make -f simulator/gcc/Makefile assets -j8    Reading ./application.config    Done  Post Generate    touchgfx update_project --project-file=simulator/msvs/Application.vcxproj    Done  Post Generate Targ...

RMuru.1 by Associate II
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Nucleo-h745ziq spi 1 and spi 3 MOSI pin mapping issue.

Hello ,I am using NUCLEO-H745ziq board. I am trying to loopbacking. SPI1 and SPI3 i am using. SPI1 as full duplex slave and SPI3 as full duplex master.Both operating on 25MHZ.But i have issue with is MOSI pin.Because PB5 is assigned to both. But when...

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MDeva.1 by Associate II
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STM32 built-in flash endurance test, targeting STM32L4R7.

Good day.Lately, I had carried out a STM32 built-in flash endurance test, targeting STM32L4R7.I selected a sector which is : Bank 2, 0x081F F000 - 0x081F FFFF, 4K, page 255to perform erase and program, with the hope that it could eventually fail. So ...

Msee by Associate
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Migrating from L4 to F4

What are the main points which I have to consider when migrating from STM32L4 to Stm32F4 apart from the connecting peripheral power management, Is there any main points which I have to consider when programming.

Roshan by Associate III
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