On the STM32U5xx, keep ADCx->CCR PRESC = 0, do not use the prescaler.
I'm using the ADC1 and ADC4 with PLL as kernel clock (MSIS 24MHz pll'ed to 32768 Hz watch crystal / 2 x (11 + 2163/8192) / 24) = 5.632 MHz). The ADC1 in combination with the MDF "looses" every second sample. The ADC4 never gets ready. The errata shee...