Is it possible to run two SDRAM (AP6404L) memories on an L5 OSPI interface?
They don't make DRAM QSPI chips in an SO-8 package with more than 64 Mbits (maps to 2 Mbytes * 32). Given the current processor shortage, I've got an application where I'd like more memory (and I'm using a 100 pin package which is quite pin limited,...