'U5 SBus-via-DCACHE1 connectivity
Is this connection real?I don't think so. DCACHE implementation subchapter says:The DCACHE1 is placed on Cortex®-M33 S-AHB bus, and caches only the external RAMmemory region (OCTOSPI, HSPI, and FMC), in the address range [0x6000 0000:0xAFFFFFFF] of t...